The present inventive concepts relate to sense amplifiers for resistive type memory circuits, and more particularly to a write driver in a sense amplifier for resistive type memory.
Resistive type memories encompass a new generation of non-volatile memory and are expected to become more prevalent in the marketplace. Resistive type memories can include, for example, spin transfer torque (STT) magnetoresistive random-access memory (MRAM), MRAM (of the non-STT variety), memristor RAM, ReRAM, CBRAM, and the like.
FIG. 1A is a circuit diagram of a typical write driver 105 in a sense amplifier for resistive type memory circuits. Referring to FIG. 1A, a latch circuit is configured by PMOS type transistors P1 and P2. NMOS type transistors N1 and N2 are driving transistors, which are larger in size (e.g., 2× larger) than the transistors P1 and P2 to provide sufficient drivability. Differential input terminals (i.e., In− and In+) are coupled to the gates of the driving transistors N1 and N2, respectively. An input voltage can have a one-half voltage swing, or in other words, the input voltage can range between the voltage potential VSS and ground potential GND, where GND is one half of the difference between VDD and VSS. However, where a one-half voltage swing on the input is used, the NMOS type transistors N1 and N2 must be significantly larger, taking up more die area. In cases where the write driver of FIG. 1A receives a full voltage swing on the input (i.e., between VDD and VSS), there still remains a stacked PMOS configuration (i.e., P0-P1 and P0-P2), which also significantly increases the consumption of die area. An output voltage fully swings between VSS and VDD.
A control signal WRa is delayed by the delay circuit 115 to produce the delayed control signal WRd. In an initial state, the control signal WRa is not asserted or is otherwise LOW and WRd is asserted or is otherwise HIGH. In the initial state, the output voltage level is undefined because the switch transistors P0 and N0 are off, which causes the latch transistors P1 and P2 and the driving transistors N1 and N2 to be in an undefined or dangling condition. In response to the control signal WRa being asserted or otherwise being set to HIGH, the control signal WRd is not asserted or is otherwise set to LOW after the delay. Depending on the voltage levels at the differential input terminals In− and In+, the latch circuit will latch, based on positive feedback, either a logical high value (e.g., ‘1’) or a logical low value (e.g., ‘0’) at the differential output terminals Out+ and Out−, respectively.
FIG. 1B is a circuit diagram of another typical write driver 110 in a sense amplifier for resistive type memory circuits. The write driver 110 is similar to that of the write driver 105, with a few notable differences. The latch circuit is configured by NMOS type transistors N1 and N2. PMOS type transistors P1 and P2 are driving transistors, which are larger in size (e.g., 8× larger) than the transistors N1 and N2 to provide sufficient drivability. The differential input terminals (e.g., In− and In+) are coupled to the gates of the driving transistors P1 and P2, respectively. An input voltage can have a one-half voltage swing, or in other words, the input voltage can range between the voltage potential VDD and ground potential GND, where GND is one half of the difference between VDD and VSS. However, where a one-half voltage swing on the input is used, the PMOS type transistors P1 and P2 must be significantly larger, taking up more die area. Similar to the Writer A of FIG. 1A, in cases where the write driver of FIG. 1B receives a full voltage swing on the input (i.e., between VDD and VSS), there still remains a stacked PMOS configuration (i.e., P0-P1 and P0-P2), which also significantly increases the consumption of die area. An output voltage fully swings between VSS and VDD.
A control signal WRb is delayed by the delay circuit 120 to produce the delayed control signal WRc. In an initial state, the control signal WRb is asserted or is otherwise HIGH and WRc is not asserted or is otherwise LOW. In the initial state, the output voltage level is undefined because the switch transistors P0 and N0 are off, which causes the latch transistors N1 and N2 and the driving transistors P1 and P2 to be in an undefined or dangling condition. In response to the control signal WRb not being asserted or otherwise being set to LOW, the control signal WRc is asserted or is otherwise set to HIGH after the delay. Similar to the write driver 105, depending on the voltage levels at the differential input terminals In− and In+, the latch circuit will latch, based on positive feedback, either a logical high value (e.g., ‘1’) or a logical low value (e.g., ‘0’) at the differential output terminals Out+ and Out−, respectively.
Because of fundamental characteristics of CMOS logic, certain circuit configurations require extensive die area, which increases the cost of the overall circuit. For example, a PMOS type transistor needs to be double the size relative to an NMOS type transistor to provide the same drivability. By way of another example, a stacked CMOS configuration where multiple transistors are serially connected requires that each transistor be four times the size relative to non-stacked transistors to achieve the same drivability. In addition, transistors receiving half of a gate voltage need to be four times the size relative to transistors receiving a full gate voltage to achieve the same drivability. Such characteristics cause the write drivers in sense amplifiers of the prior art to consume undesirable amounts of die area.
Accordingly, a need remains for improved write drivers, which consume less die area and use fewer control signals, and therefore, provide more compact and less expensive circuits.